Functional test method for asynchronous sequential circuits

ABSTRACT

A METHOD FOR TESTING PHYSICAL SEQUENTIAL LOGIC CIRCUITS INCLUDING A PROGRAM STEP FOR CONTROLLING A COMPUTER TO GENERATE TEST PATTERNS FOR USE IN LOCATING PERMANENT FAULTS IN PHYSICAL SEQUENTIAL LOGIC CIRCUITS BUILT FOR USE IN DIGITAL EQUIPMENT BY PROVIDING A METHOD FOR FINDING FEEDBACK LOOPS AND IDENTIFYING AN APPROPRIATE LINE IN THE LOOP TO     TERNS, AND APPLYING THE TEST PATTERNS TO THE PHYSICAL SEQUENTIAL CIRCUIT.   CUT, AT LEAS FIGURATIVELY, IN ORDER TO CONVERT A REPRESENTATION OF THE PHYSICAL SEQUENTIAL CIRCUIT TO A REPRESENTATION OF AN EQUIVALENT COMBINATIONAL CIRCUIT, ANALYZING THE RESULTANT COMBINATION CIRCUIT REPRESENTATION ACCORDING TO SPECIFIC BOOLEAN RULES TO OBTAIN A COMPLETE SET OF TEST PAT- D R A W I N G

A DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with" the Notice of Dec. 16, 1969. 869 0.6. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of eachiabstract indicates the number of pages of specification. including claims and sheets of drawings contained in the application as originally filed. The flies of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Ofllce makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED JULYQ, 1974 T924,006 FUNCTIONAL TEST METHOD FOR ASYNCHRO- NOUS SEQUENTIAL'CIRCUITS INPUT Dennis K. Chin, Wappingers Falls, and S e-June Hong, mm mm" a. ii Mu-Yue Hsiao, and Darryl S. Jones, Poughkeepsie, DESCRIPTION I20 N.Y., and Jung W. C110, 8820 Root St., Apt. 4, Niles, I.-

oop CUTTER Continuation of abandoned application Ser. No. 256,554, Mm cm i May 24, 1972. This application Oct. 3, 1973, SCI. N0- FEEDBACK oops 403 144 m r e ci cosr 11/1 24) Cl. 35-153 5 Sheets Drawing. 24 Pages Specification m5) wima f i mm mm DETERMINE man 6 s E H4 soumons m A. 1- TEST PATTERN LOG"; CIRCUIT I FORA THE CITTOUITN I GENERATION DESCRIPTION l L H m us TRACE m was m rnol OUTPUT T0 mm INPUT i mm NEETETPNEN OUTPUT UNDER TEST FOR EACH W \m l GENERATE PAIR or TEST RESULT TEST PATTERNS 6 A method for testing physical sequential logic circuits m (2 including a program step for controlling a computer to i generate test patterns for use in locating permanent faults T J 'g g in physical sequential logic circuits built for use in digital m LOGIC cmcun' m equipment by providing a method for finding feedback loops and identifying an appropriate line in the loop to but (Table continued on page 2)] (FROM HOS) LOOP CUTTER PATIIGEN OENERATE -A TABLE or was m PORN A LOOP TABLE INCLUDING LOOP OISTANOE ORDER LOOPS BY DESOENOINC DISTANCE SELECT LOOP mu LONGEST msmacs OUT LOOP ONE LINE AIAY FRONLAST ENTRY ON LOOP TREE DELETE ALL LOOPS rnon LOOP TABLE THAT comm um; our m UPDATE PREOECESSOR LIST cut, at least figuratively, in order to convert a representw tiOn of the physical sequential circuit to a representation of an equivalent combinational circuit, analyzing the resultant combinational circuit representation according to specific boolean rules to obtain a complete set of test pat- PATIICEII STORE OUTPUT LINE mm m INSPECT PREOECESSOR LIST FEELEETEAST on usr IIO FIOSI 5m: rnrorcrsson was m PATH szourncr terns, and applying the test patterns to the physical sequential circuit.

' July 2, 1974 FUNCTIONAL TEST METHOD FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS Original Filed May 24, 1972 D. K. CHlA ETAL 5 Sheets-Sheet 1 TEsT PATTERN LOGIC CIRCUIT l I GENERATION DESCRIPTION INPUT LOGIC CIRCUIT TESTER 4 OUTPUT UNDER TEST TEsT RESULT A F l G 7 E H Y; .9,, AND E AND F I G 8 54 A l OR 58 52 AND A AND 55 54 G D L 0R July 2, 1914 FUNCTIONAL TEST METHOD FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS Original Filed May 24, 1972 D. K. cum ETAL T T924306 5 Sheets-Sheet 3 FIG.2

(FROM FICS) NOTE FEEDBACK VARIABLES & DETERMINE THEIR EQUATIONS \122 HOMING SEQUENCE CENERATE A BOOLEAN EXPRESSION FOR THE CIRCUIT TRACE ALL PATHS FROM OUTPUT TO INPUT CENERATE BOOLEAN DIFFERENCE CHAIN FOR EACH PATH CENERATE PAIR OF TEST PATTERNS FOR EACH PATH PREPARE LIST OF TEST PATTERNS FOR LOCIC CIRCUIT July 2, 1974 I c ETAL T924,06

FUNCTIONAL TEST METHOD FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS Original Filed May 24, 1972 5 Sheets-shat 3 2 5 20 FIG. 3

NOR L 0R NOR MAN!) 42 H 49 OR 9 NOR \NoR OUTPUT 1 8 u NOR l 3 46 NOR 7 25 July 2, 1914 Q HIA EI'AL T924,006

FUNCTIONAL TEST HETBOD FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS Original Filed May 24, 1972 5 Sheets Sheet A LOOP CUTTER PATHGEN CENERATE A TABLE OF PATHS \IZII FROM FIG 6 FORM A LOOP TABLE INCLUDING LOOP DISTANCE \442 ORDER LOOPS B DESCENDING DISTANCE 443 I SELECT LOOP IIIITH LONGEST DISTANCE 444 CUT LOOP ONE LINE AWAY FROM LAST ENTRY ON LOOP TREE DELETE ALL LOOPS FROM LOOP TABLE THAT comm LINE CUT I4e UPDATE PREDECESSOR LIST 47 YES ANY REMAINING July 2, 1974 K cH EIAL T924,06

FUNCTIONAL TEST METHOD FOR ASYNCHRONOUS SEQUENTIAL CIRCUITS Original Filed May 24, 1972 5 Sheets-Sheet 5 F I G. 6

PATHGEN INSPECT PREDECESSOR usr I5I MULTIPLE SELECT FIRST & SELECT LAST PREDECESSORS LIST OTHERS 0N LIST ANY 5 STORED PREDECESSORS IS PREDECESSOR A PRIMARY INPUT VSTORE LINE NUMBER IS PREDECESSOR LINE ALREADY IN PATH FLAG FEEDBACK PATH STORE PREDECESSOR LINE IN PATH SEQUENCE 455 

